林哲
一、个人简介
林哲，中山大学“百人计划”副教授，深圳市海外高层次人才，2023-2025连续三年集创赛国赛优秀指导教师，2025年度中山大学优秀辅导员，2025年度中山大学优秀社团指导教师。长期从事芯片设计自动化（EDA）及可重构异构芯片与系统（FPGA+NPU+CPU）研究。主持国家级、省部级、市厅级、校企横向等科研项目累计10余项。以第一/通讯作者发表集成电路领域高水平期刊/会议论文20余篇，获得旗舰学术会议ICCD 2024、DATE 2022、FCCM 2019最佳论文奖提名。担任多个旗舰学术会议（如DAC、DATE、ASP-DAC）的技术程序委员会（TPC）成员。获得授权发明专利7项。指导本科生团队获得集创赛全国一等奖、FPGA竞赛全国二等奖等多个国家级奖项。
林哲创建了异构芯片与系统设计自动化课题组，为课题组的每名研究生定制详细的研究课题，定期开展单独的科研辅导。欢迎对数字集成电路设计自动化、计算机体系结构方向感兴趣并愿意付出努力的同学联系！
联系邮箱：linzh235@mail.sysu.edu.cn
科研追踪：https://zlinaf.github.io/
二、研究领域
1. 数字芯片设计自动化
芯片设计自动化（EDA）是利用计算机科学理论和软件工具，将系统需求逐级转化为电路、版图并最终完成流片制造的全过程，使大规模复杂芯片能够高效、可靠地从“想法”走向“实体”。课题组围绕数字集成芯片及系统的EDA前端流程（从架构设计或高层级编程语言到硬件描述语言及门级网表），重点研究如何实现芯片的能效比自动优化，同时降低芯片设计时间开销。典型工作包括：面向C/C++编程语言和高层次综合的早期功耗建模方法，融合人工先验与重要性引导的大规模设计空间探索方法，以及深度学习驱动的逻辑综合优化方法。
2. 可重构异构芯片与系统
随着半导体制造技术接近物理极限，传统以中央处理器（CPU）为核心的同构计算体系难以满足大数据算力需求，异构计算由此兴起。可重构异构计算系统集成了可编程逻辑门阵列（FPGA）、神经网络处理器（NPU）等可重构或异构加速器，与CPU协同执行计算密集型任务。课题组研究可重构异构芯片及系统的软硬件设计方法，涵盖系统及互联架构设计、编译工具链、领域定制加速器等。典型工作包括：面向大规模AI场景的多粒度异构编译优化，面向AMD Versal ACAP异构计算平台的矩阵奇异值分解（SVD）、稀疏矩阵乘法（SpGEMM）加速器。
三、教育背景
2014.09-2020.01，香港科技大学，博士；
2010.09-2014.06，东南大学，学士。
四、工作经历
2026.01至今，中山大学，副教授、硕士生导师；
2023.03-2026.01 ，中山大学，助理教授、硕士生导师；
2020.03-2023.02，鹏城实验室，助理研究员、副研究员。
五、代表性科研项目
1. 国家自然科学基金青年项目，2025.01 – 2027.12，主持。
2. 广东省自然科学基金面上项目，2024.01 – 2026.12，主持。
3. 广东省自然科学区域联合基金-青年基金项目，2023.11 – 2026.10，主持。
4. 深圳自然科学基金面上项目，2025.10 – 2028.10，主持。
5. 深圳市优秀科技创新人才培养项目-青年项目，2024.06 – 2026.06，主持。
6. 华为校企合作项目，2024.10 – 2025.12，主持。
六、部分代表性成果
*表示通讯作者，#表示本人指导的中大学生
2026
[DATE] Yingxin Zeng#, Binghao Cheng#, Jianwang Zhai, Kang Zhao, Zhe Lin*. “AutoShrink: Adaptive Search Space Shrinkage for Large-Scale Pareto Optimization of HLS Designs.” In Proc. of Design, Automation and Test in Europe Conference (DATE), 2026.
[ICC] Lihe Liang#, Xiao Yun#, Kuangxun Huang#, Zhe Lin*, Zhongfeng Wang*. “JIMI: A Hierarchical Partition-Refinement MIQP Framework for Jitter Minimization in PONs.” In Proc. of IEEE International Conference on Communications (ICC), 2026.
[ASP-DAC] Zibo Hu, Zhe Lin*, Renjing Hou, Xingyu Qin, Jianwang Zhai, Kang Zhao*. “HLS-Timer: Fine-Grained Path-Level Timing Estimation for High-Level Synthesis.” In Proc. of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2026.
2025
[TCAD] Sen Yan#, Kuangxun Huang#, Kang Zhao, Zhe Lin*. “Accurate, Efficient and Scalable Power Modeling for FPGA HLS.” In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.
[ICCAD] Zefan Lin#, Zedong Peng, Mingzhe Gao, Jieru Zhao*, Zhe Lin*. “HIPPO: A Hierarchy-Preserving and Noise-Tolerant Pre-HLS Power Modeling Framework for FPGA.” In Proc. of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2025.
[ICPADS] Kuangxun Huang#, Xiao Yun#, Lihe Liang#, Zhe Lin*. “DARE: Towards Maximized Bandwidth Utilization of Dynamic Bandwidth Allocation for Next-Generation Passive Optical Networks.” In Proc. of International Conference on Parallel and Distributed Systems (ICPADS), 2025.
[DAC] Xinya Luan, Zhe Lin*, Kai Shi, Jianwang Zhai and Kang Zhao*. “HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design.” In Proc. of ACM/IEEE 62nd Design Automation Conference (DAC), 2025.
[DAC] Kai Shi, Zhe Lin*, Xinya Luan, Jianwang Zhai and Kang Zhao*. “VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration.” In Proc. of ACM/IEEE 62nd Design Automation Conference (DAC), 2025.
[FPT] Liyang Dou, Zhe Lin*, Kai Shi, Xinya Luan, Kang Zhao*. “An End-to-End Tool Flow with Intrinsic-Level Kernel Optimization on Versal ACAP.” In Proc. of International Conference on Field Programmable Technology (FPT), 2025.
2024
[ICCD] Mingzhe Gao, Jieru Zhao*, Zhe Lin*, Wenchao Ding, Xiaofeng Hou, Yu Feng, Chao Li, Minyi Guo. “AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs.” In Proc. of IEEE International Conference on Computer Design (ICCD), 2024. IEEE ICCD 2024最佳论文提名
[DATE] Mingzhe Gao, Jieru Zhao*, Zhe Lin*, Minyi Guo. “Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs.” In Proc. of Design, Automation and Test in Europe Conference (DATE), 2024.
2023及之前
[TCAD] Zhe Lin, Tingyuan Liang, Jieru Zhao, Sharad Sinha and Wei Zhang. “HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS.” In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023.
[DATE] Zhe Lin, Zike Yuan, Jieru Zhao, Wei Zhang, Hui Wang and Yonghong Tian. “PowerGear: Early-stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs.” In Proc. of IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1341-1346, 2022. IEEE DATE 2022最佳论文提名
[TCAD] Zhe Lin, Sharad Sinha and Wei Zhang. “Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System.” In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 40, no. 11, pp. 2279-2292, 2021.
[ASPDAC] Zhe Lin, Jieru Zhao, Sharad Sinha and Wei Zhang. “HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis.” In Proc. of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 574-580, 2020.
[TCAD] Zhe Lin, Sharad Sinha and Wei Zhang. “An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power.” In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 38, no. 9, pp. 1661-1674, 2019.
[FCCM] Zhe Lin, Sharad Sinha and Wei Zhang. “Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA.” In Proc. of IEEE Field-Programmable Custom Computing Machines (FCCM), pp. 172-180, 2019. IEEE FCCM 2019最佳论文提名
[TMSCS] Zhe Lin, Sharad Sinha, Hao Liang, Liang Feng and Wei Zhang. “Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors.” In IEEE Transactions on Multi-Scale Computing Systems (TMSCS), vol. 4, no. 2, pp. 152-162, 2018.
[FPL] Zhe Lin, Wei Zhang and Sharad Sinha. “Decision Tree Based Hardware Power Monitoring for Run Time Dynamic Power Management in FPGA.” In Proc. of IEEE International Conference on Field Programmable Logic and Applications (FPL), pp. 1-8, 2017.